A semiconductor wafer is processed by a semiconductor manufacturer to form various integrated circuits (IC) in different regions of the wafer. Variations in pattern density over the different regions can cause various issues including critical dimension (CD) variation or CD uniformity. When the semiconductor fabrication scales down to increasingly advanced technology nodes, such as 45 nm, 32 nm, or 28 nm, the IC features are more sensitive to CD variations and uniformity. For example, dense lines and isolated lines are common in IC layout and cannot be avoided by the design rules. However, as the feature size decreases, high fidelity replication of such mask features into an underlying material layer can be problematic. Additionally, as the technologies have advance, some currently used approaches may have limited effectiveness and applicability. Therefore, there is a need of a masks and methods to address such issues.